Design for Testability (DFT) Architect
Aeva, Inc., United States

• As an SoC DFT Architect you’ll be responsible for defining and/or overseeing, advanced design-for-test (DFT) methodologies for highly-complex digital and/or mixed-signal chips and/or IPs. You will have the opportunity to work with the rest of the team to document DFT specifications, and also develop DFT methodologies and infrastructure. In this role, you'll oversee the definition, development and verification of a consistent methodology for DFT across the whole SoC.

• 2-5 years’ experience writing RTL code in Verilog and/or VHDL
• 2-5 years of verification experience
• Broad domain knowledge of DFT including Scan/ATPG, MBiST, LBiST, JTAG, TAP, IO BiST, Analog BiST, etc..
• In depth knowledge of EDA tools used in DFT.
• Lab debug and DFT bringup experience
• Ability to deliver results in a very fast-moving environment
• Desire to learn amp; implement groundbreaking new hardware technology
• Excellent communication and organization skills.

• Functional Safety Experience

• Be part of a fast paced and dynamic team
• Very competitive compensation and meaningful stock grants
• Exceptional benefits: Medical, Dental, Vision, and more
• Unlimited PTO: We care about results, not punching timecards

Job Rewards and Benefits